3. Digital Microelectronics VLSI Design

EC ENGR 870.03

This course covers design approach and techniques to optimize for speed, area and power for Very Large Scale Integrated (VLSI) digital circuits from design to physical layout.

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This course covers design approach and techniques to optimize for speed, area and power for Very Large Scale Integrated (VLSI) digital circuits from design to physical layout. It examines microelectronics design, MOS transistor characterization, non-ideal behaviors, fabrication processes, design rules, multi-layer interconnect engineering and modeling, standard and custom cell layout. It addresses design optimization techniques to minimize power, minimize area and maximize speed. It will cover basic digital circuits, and planar and FinFet technologies. It provides a condensed and focused look at VLSI chip design for the 21st century, something that every chip designer must be aware of.

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