Design for Testability and for Built-In Self Test

EC ENGR 870.10

Gain a comprehensive treatment of testability for all manifestations of electronics. Explore the techniques that to provide built-in self-test (BIST) capabilities – not only at the IC level but also at the board and system levels as well.

READ MORE ABOUT THIS COURSE
Remote
Starting at $1,495.00
As few as 2 weeks
1.8

What you can learn.

  • Understand the cost/benefit analysis of tests and overcoming difficulties through easier to test designs
  • Gain a working knowledge of both ad hoc and structured DFT for ICs, boards and systems
  • Evaluate the use of the JTAG/IEEE-1149.1 Boundary Scan and several similar mechanisms
  • Determine several BIST techniques and architectures and know which apply best to circuits they are developing
  • Gain confidence to tackle the most complex circuits and make them easily testable

About this course:

The course discovers the need for a new paradigm, by which designs and tests are developed in parallel, resulting in earlier time to market, higher failure detection and lower test costs. It presents simple techniques to improve observability and controllability of any circuit. Designers can readily follow such guidelines. Moreover, the course examines structured scan techniques standardized by the IEEE-1149.1 (JTAG), by other IEEE-1149.x, by the IEEE-1500, by IEEE-1687 and by the proposed IEEE-P1687.1, 1687.2 and P2653 working groups. A thorough understanding of these techniques for testability leads to similar BIST structures. The course covers memory BIST (MBIST), logic BIST (LBIST) and analog BIST. Learn built-in test (BIT) software, and its goal to provide diagnostic information as well. The course also teaches the need at system-level to provide repair instructions through module replacement. In order to achieve the unambiguous isolation of the faulty circuits’ testability has to be assessed at the design stage – often before the circuit details are known. Explore how this can be achieved using diagnostic assessment and modeling techniques. Finally, the course evaluates the value of DFT and BIST at all levels of assembly from an economic perspective. Attendees gain a thorough understanding of the techniques and with the tools necessary to convince management that DFT and BIST will profit both manufacturing and support, while at the same time greatly improve the quality of units under test UUTs. The course is primarily for designers and test engineers and provides great value to reliability, logistics, quality and manufacturing engineers as well. Managers concerned with testability and BIST techniques as well as those with general interest on IEEE and military standards in DFT also benefit from this course.
Prerequisites
 

This course requires attendees to have an understanding of basic circuit elements such as logic gates, flip-flops and multiplexers.

 

Fall 2021 Schedule

Date & Time
Details
Format
 
-
Monday, Wednesday, Friday 8:00AM - 11:00AM PT
Available
See Details
Instructor: Louis Ungar
383479
Fee:
$1,495.00
Remoteformat icon
Location: Online
ENROLL BY: Nov 1, 2021
See Details
Notes

Contact
Joon Lee
(310) 206-3858
jlee@unex.ucla.edu

 

Refund Deadline
No refunds after November 02, 2021
Schedule
Type
Date
Time
Location
Lecture
Mon Nov 1, 2021
8:00AM PT - 11:00AM PT
Online
Lecture
Wed Nov 3, 2021
8:00AM PT - 11:00AM PT
Online
Lecture
Fri Nov 5, 2021
8:00AM PT - 11:00AM PT
Online
Lecture
Mon Nov 8, 2021
8:00AM PT - 11:00AM PT
Online
Lecture
Wed Nov 10, 2021
8:00AM PT - 11:00AM PT
Online
Lecture
Fri Nov 12, 2021
8:00AM PT - 11:00AM PT
Online

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